Tuesday, May 12, 2009

TSMC's New Business Model

(I hope)

Let their customers bypass both Cadence and Mentor. Here's what they need to do :

Download Berkeley spice and customize it and robustize it - ensure no non-convergence issues with their models. Cost ~300k, time ~ 1 yr, 4 people.

Download the open-source EDA tools for schematic and layout and customize them and professionalize them. Cost ~4 million, time ~ 1 yr, 30 people. Might want to subcon here.

Then, generate libraries that your customers can use - standard cell digital libraries and also some analog stuff - voltage references, regulators, VCOs, etc. These must be proven on silicon and macromodels that can be used with the simulator should be available. The IP should be provided too - so customers can tweak. This is akin to Cadence providing ahdlLib. Cost ~40 million, time ~ 2 yrs, 40 people.

Then, customize the simulator and design environment to make models transparent to the user. The user should never have to worry about models and should also never be able to look at the models. Of course, the user can rig up the simulation to get the characteristics of the devices and thereby write his own model for use with another simulator, but the effort should be unnecessary. Cost ~10 million, time ~ 1 yr, 10 people.

Now, let people download the tool and libraries from your website for free. They can now try out designs and see if they work and if they work in simulation, can go search for funding to get the chips fab'd/manufactured.

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